To implant dopants in junctions of a semiconductor device, plasma doping (“PLAD”) (also known as plasma immersion ion implantation (“PIII”)) and beamline ion implantation have been used. Beamline ion implantation is a high energy implantation technique where ions penetrate deeply into a substrate, semiconductor wafer, or other workpiece. In contrast, PLAD has unique advantages including system simplicity, lower cost and higher throughput.
In PLAD, the substrate is implanted with a dopant, such as boron (p-type dopant), arsenic (n-type dopant), or phosphorus (n-type dopant). The substrate is placed on a conductive platen, which functions as a cathode. A gaseous precursor to the dopant is introduced into a chamber and a voltage pulse is applied between the conductive platen and an anode or the chamber walls. Voltage pulse or other sources such as RF or microwave generate plasma and form a plasma sheath at the surface of the substrate. The applied voltage causes ions in the plasma to cross the plasma sheath and to be implanted into the substrate. The depth of implantation is related to the voltage applied between the substrate and the anode. Ultrashallow junctions are achieved using a low implant energy, such as an energy that ranges from approximately 50 eV to approximately 10 keV with a dose greater than 1 e15/cm2.
The dopant is implanted into desired locations on the substrate containing a photoresist layer, which has been developed and etched to form a desired pattern. The photoresist layer functions as a mask and prevents the dopant from penetrating portions of the substrate covered by the photoresist layer while the dopant penetrates the exposed portions of the substrate. However, during implantation, the dopant may deposit on the photoresist layer, forming a film on a surface thereof. During subsequent processing, the photoresist layer is difficult to remove from the substrate due to the presence of the dopant-containing layer and a carbon-rich crust on the photoresist layer. For instance, the photoresist layer is not effectively removed by a conventional post-implant strip and cleaning process, such as a plasma strip process that utilizes oxygen gas (“O2”) with a forming gas (approximately 4% hydrogen (“H2”) in nitrogen (“N2”)). This post-implant strip and cleaning process is conducted at a microwave power of approximately 2000 W, a temperature of approximately 300° C., and an exposure time of 50 seconds and is referred to herein as the “O2 plasma strip.” During the O2 plasma strip, “popping” of the photoresist layer occurs, producing significant amounts of photoresist residuals that remain on the substrate and form the carbon-rich crust.
For instance, if the implanted dopant is boron, a boron-containing (“B-containing”) layer may form on the substrate during implantation depending on process conditions. The B-containing layer is a film of a nonvolatile, boron, boron oxide (“B2O3”) or a mixture thereof that covers the photoresist layer and prevents removal of the photoresist layer using the O2 plasma strip. Although several alternatives have been developed to minimize or control the formation of the B-containing layer, the B-containing layer continues to be deposited on the photoresist layer under certain implantation conditions. Currently, the best alternative for removing the B-containing layer is to expose the substrate to a Piranha solution, an SC1 (RCA1) solution, a hydrogen fluoride solution, or mixtures thereof. Piranha is also known as “SPM” (Sulfuric Acid and Hydrogen Peroxide Mixture). The normal processing temperature is approximately 100-150° C. “SC1” is also known as “APM” or Ammonium Hydroxide and Hydrogen Peroxide Mixture. Hydrogen fluoride is typically provided in a ratio with deionized water of 100:1 to 500:1 However, these solutions cause streaking defects across the substrate, which leads to downstream processing problems.
PLAD and beamline ion implantation are commonly used to produce source/drain regions in complementary metal-oxide-semiconductor (“CMOS”) transistors. However, one difficulty with CMOS processing is achieving increasingly shallow source/drain junctions while maintaining predictable and desired performance of the CMOS transistor. As the dimensions of CMOS transistors become smaller, it is becoming harder to form shallow junctions while maintaining or improving overall performance of the CMOS transistors. As the sizes of semiconductor devices decrease, low energy implant processes are needed to form features on the semiconductor device, such as CMOS transistors. For instance, to prevent current leakage in small-scale transistors, techniques for forming ultrashallow junctions having a depth of less than approximately 50 Å-500 Å, typically 200 Å from a top surface of the substrate and a high fraction of dopants in an unclustered state are needed. Due to the low energy and shallow implantation available with PLAD, PLAD is replacing beamline ion implantation in the formation of ultrashallow junctions. PLAD is also advantageous to beamline implantation due to its system simplicity, lower cost, and higher throughput. However, PLAD is a more complicated process than beamline implantation because of its plasma environment and non-mass-analyzed feature.